https://irds.ieee.org/images/files/pdf/2024/2024IRDS_LITHO.pdf
< Lithography and patterning technology have continued to advance but still face many challenges. EUV exposure tools with a
numerical aperture (NA) of 0.55 started being delivered to customers at the end of 2023. First production use of such tools is
projected for 2027. The availability of both multiple patterning and high NA EUV enables high resolution patterning that already
can meet resolution requirements through 2029. Resolution should be extendable to meet requirements through 2033, where
minimum metal half-pitch is expected to be 7 nm, and the minimum via pitch is expected to be 31 nm. However, achieving this
resolution does not mean lithography requirements are satisfied. Improvements in control of stochastic issues such as defects
and line edge roughness are substantial current challenges. Advances in light sources, in mask design, in mask materials, in
photoresists, and in ancillary materials such as underlayers will be needed along with improvements in defectivity. All of these
will be needed to accommodate the limited depth-of-focus of high NA imaging. Another issue with high NA EUV is the field
size, which is half that of the 0.33 NA tools currently used in production. High performance systems that have used large chips
in the past will have options to keep improving performance. Two or more exposures for different parts of a chip can be used
with the patterns stitched together, or can be used packaging to connect smaller chips and provide high performance overall.
Both options have their challenges. Packaging connection pitches will need to shrink to provide improved connectivity as shown
below, but larger chips may still be made using stitching, with its attendant challenges. As an alternative, larger format EUV
masks are being considered for enabling the patterning of large chips with single exposures.
< Starting in 2025, there will be metal lines and spaces patterned on the back of the chip to enable smaller logic unit cells. This
will start with four backside layers of metal using 193 nm lithography that provide power distribution and I/O. In 2027 the
backside metal will start being patterned with EUV and include more chip functions. 3D logic devices with one or more layers
of devices stacked on top of each other are projected to be introduced in 2035 and after that there is little change in minimum
chip dimensions.
< In the long term, there are some possible new technologies being evaluated to meet these requirements. EUV phase shifting
masks, curvilinear mask designs, free electron lasers as a possible light sources, larger mask sizes, directed self-assembly for
pattern rectification, and new device designs and process integration are all being investigated. Hyper NA EUV tools with NA’s
above 0.75 are being considered to improve process windows. New resists based on metals are being actively investigated.
Metal resist has the potential to enable thinner films that still absorb sufficient light and provide usable etch resistance. Shorter
wavelengths than the current 13.5 nm are also being investigated but their use is farther off than improved NA. Sustainability is
also a long-term challenge. Improved materials and reduced power and water usage will be needed